1. Field of the Invention
The present invention relates to a signal processing circuit of a disc reproduction apparatus such as a disc player for reproducing digital audio discs referred to as compact discs (CDs) or MiniDiscs (MDs) and other information recording discs (hereinafter simply referred to as discs).
2. Description of the Related Art
In digital audio discs, for example, CD types of discs, use is being made of the modulation system referred to as a "eight to fourteen modulation" (EFM). When demodulating this EFM signal, a clock (hereinafter simply referred to as a reproduction clock) is generated based on a binary pulse train signal obtained by waveform-shaping a RF signal read from the disc. The demodulation is carried out by using this reproduction clock. To generate this reproduction clock, generally a phase locked loop (PLL) circuit has been used.
It has also been required that this PLL circuit be able to be used in a frequency bandwidth with a wide oscillation frequency.
For example, the CD-ROM market is moving in the direction of higher speed reproduction. The signal processing large-scale integrated circuits (LSIs) (for example, digital signal processors) used for CD-ROMs are being required to be capable of super-high speed n-multiple speed for realizing higher speed reproduction than standard one speed, for example, up to 16.times. speed or 24.times. speed. In the signal processing LSIs for CD-ROMs, in order to obtain the required oscillation frequency, it is necessary to include a high voltage-controlled oscillator (VCO) for the maximum oscillation frequency.
FIG. 1 is a block diagram of an example of the basic configuration of a PLL circuit used for the generation of a reproduction clock.
In FIG. 1, the oscillation frequency of a crystal oscillator 11 (for example, 16.9344 MHz) is divided by M (M is an integer) at a prescaler 12 and becomes one input of a phase comparator 13. The phase comparator 13 receives as another input a frequency signal obtained by dividing the oscillation frequency of the VCO 14 by N (N is an integer) at a prescaler 15, compares the phases of the two frequency signals, and outputs a phase difference signal thereof. This phase difference signal passes through a low pass filter (LPF) 16 and becomes the control voltage of the VCO 14. The VCO 14 changes in its oscillation frequency in accordance with this control voltage. The oscillation output of this VCO 14 is derived as a reference clock of L (integer) times the finally obtained reproduction clock PLLCK and, at the same time, becomes the other input of the phase comparator 13 through the prescaler 15.
In this circuit configuration, the circuit operates so that phases of the two input signals of the phase comparator 13 coincide. As a result, the frequencies of two input signals will also coincide.
Note that, the oscillation frequency 16.9344 MHz of the crystal oscillator 11 becomes 384.times.fs where a sampling frequency fs is set to the same frequency as that of the CD system, that is, 44.1 kHz.
Further, when setting the frequency of the reproduction clock PLLCK at 4.3218 MHz, the 4.3218 MHz is the channel clock frequency at the time of PWM modulation of the EFM signal by the CD method. The EFM signal is PWM modulated in a 1 period step from the 3 periods to 11 periods.
A reference clock having a frequency L times the channel clock is given to a digital PLL circuit 22. The digital PLL circuit 22 is comprised of a frequency error counting circuit 17, a low pass filter 18, a phase error counting circuit 19, an adder 20, and a digital VCO 21. It is configured to generate a reproduction clock PLLCK based on the reference clock, detects the frequency error and phase error of the EFM signal with respect to the reproduction clock PLLCK, and controls the frequency and phase of the reproduction clock PLLCK based on this frequency error and phase error.
Here, an EFM signal is a signal obtained by waveform shaping and converting to a binary format the RF signal read from the disc. This binary signal changes by nT (where, n is an integer from 3 to 11) when the period of the channel clock is T.
This digital PLL circuit 22 has a .+-.5% capture range with respect to the reference frequencies of the different speeds.
FIG. 2 is a view of the capture range at the time of different operating speeds, that is, standard speed, 2.times. speed, 3.times. speed, and 4.times. speed, of the digital PLL circuit 22.
Here, for example, considered by the reproduction clock PLLCK for measuring the period of the RF signal read from the disc (at the time of standard speed, 4.3218 MHz), the capture range of the digital PLL circuit is given by the following relation: EQU 4.3218 MHz.times.0.95.ltoreq.PLLCK.ltoreq.4.3218 MHz.times.1.05(1)
Therefore, with the above configuration, when the speed of the disc is out of the above range, PLL was not locked and it was necessary to wait until the .+-.5% range was entered.
Namely, as shown in FIG. 2, the PLL is locked within a range of .+-.5% from the fixed reference frequency, for example, at 4.3218 MHz .+-.5% at standard speed, at 8.6438 MHz .+-.5% at 2.times. speed, and at 17.2872 MHz .+-.5% at 4.times. speed, and is not locked in ranges other than this (in the figure, the range indicated by PLL Unlock).
In the circuit of FIG. 1 having such a characteristic, in a state where for example a CD player is being used outdoors, when the player is rotated in a rotation direction or an inverse rotation direction of the disc, the rotational speed of the spindle will deviate by a large amount from the target speed due to the large deviation of the relative speed with respect to the pick-up due to the inertia of the rotational movement and will no longer be in the capture/lock range .+-.f. Therefore, there were disadvantages such as a susceptibility to rotary outer disturbances, for example, unlocking of the PLL and cessation of the music, and difficulty of high speed access.
Therefore, the assignee previously proposed a signal processing circuit in which the reference frequency was made to track the rotational speed of the disc (Japanese Patent Application No. 6-291459).
In this circuit, as shown in FIG. 3, the rotational speed of the spindle motor is detected based on the EFM signal at a rotational speed counting circuit 23, a control signal for making a speed error with respect to the reference speed zero is generated, and the control signal is processed to cut its high frequency component at a low pass filter 24 and supplied to a VCO 25 as the control voltage thereof. The VCO 25 is used as a means for giving the reference frequency to an analog PLL circuit 10. A control voltage in accordance with the speed error with respect to the reference speed of the rotational speed of the spindle is given to this VCO 25, while a reference clock PLLCK.times.L is generated at the analog PLL circuit 10 based on the oscillation frequency given by this VCO 25. At the same time, a reproduction clock PLLCK is generated at a digital PLL circuit 22 based on this reference clock.
In this circuit, both of the VCO 25 and the VCO 14 in the analog PLL circuit 10 change in their oscillation frequencies in proportion to the rotational speed of the spindle. Namely, the slower the rotation, the lower the reference frequency, while the faster the rotation, the higher the reference frequency.
Since the reference frequency tracks the rotational speed in this way and the digital PLL circuit 22 has a capture range of .+-.5% with respect to the reference frequency, as shown in FIG. 4, a PLL circuit with a very wide capture range as a whole can be realized and it became possible to track any rotational speed.
As a result, when for example a disc player is being used outdoors, even in a case when the rotational speed of the spindle deviates by a large amount from the target value, for example, a case where the player is rotated in the rotation direction or reverse rotation direction of the disc and a case where a large track jump occurs at the time of access, the lock of the PLL is almost never lost, therefore there are the advantages that the data can be always read and, at the same time, high speed access becomes possible.
In a circuit adopting the so-called wide capture system of FIG. 3, however, once the PLL is lost at the time of access or the like, as shown in FIG. 5, an output signal S23 of the rotational speed counting circuit 23 for controlling the VCO 25 becomes a signal having no meaning of the high level (H) or the low level (L).
For this reason, the waveform of the output signal S24 of the latter stage LPF 24 becomes fixed to the high level or low level after passing a transition period.
This signal S24 is the control voltage of the VCO 25, but when this control voltage becomes fixed at a high level or low level, the oscillation frequency of the VCO 25 becomes minimum or maximum.
In the circuit of FIG. 3, this oscillation clock becomes an internal master clock, a PLL pull-in operation is started from a position far away from the desired oscillation frequency.
On the other hand, in addition, since the time constant of the LPF 24 used here is large, as shown in FIG. 5, a long time of an ms order was necessary for the oscillation frequency of the VCO 25 to reach the desired value.
Namely, a long time was taken from when the pick-up landed at the target track to when the PLL pull-in was terminated and locked.
In order to solve this problem, the configuration was adopted of controlling the oscillation frequency of the VCO of the rotation tracking PLL circuit by injecting a pulse from a microcomputer or the like during a traverse, but the change of characteristic of the VCO due to a solid difference of the LSI and the environment of use is large, so it has been difficult to indiscriminately control this.